CLEO III RICH test beam DAQ

For the time being this page is just a plain depository of all kinds of stuff on the RICH test beam DAQ.

Eventually, I might actually get around to producing some coherence among the noise.

Data structure for RICH Testbeam at FERMILAB November 1996. (This is not yet official !!! Once official, it will become DAQ Note 7)

Charlie's latest Orchad drawings (frequently updated) can be found here:

  • Charlie's RICH databoard WWW page.

    Frank has written a number of documents which are probably all outdated by the time you read this. Within the next few weeks (months? years?) he may or may not get around to updating at least some of the information in these documents:

  • Address map for CSR and CR space.
  • Address map for A32 address space.
  • Local protocol on the data board.
  • Some thoughts on trigger and busy (May 2nd).
  • A first attempt on writing a manual for the vmechip (May 23rd)

    Frank's *.tdf and *.vec files for vmechip design:

  • Top level tdf file for vmechip
  • the state machines in the chip
  • Control and Status Register
  • decoder for vmechip
  • cblt32 and cblt64 for vmechip.
  • Initialization tdf
  • MultiCaST
  • ADDMEM
  • Local bus arbitration
  • Vector files to test the whole design: cblt32, this file tests cblt32. cblt64, this file tests cblt64. There a files called test64.scf and test32.scf (i.e. binary files) in /home/axp/fkw/ at Cornell. These are scf files that correspond to the *.vec files above, except that I shrunk sets of nodes into groups to make the output more legible.

    The SCF files have the complete simulated wave form. They are therefore useful to compare the output you get with the output FKW got, using the Altera chip EPM7256ERC208-12.

  • More files might appear as times goes on.

    Last Updated: 30 July 1996.
    Comments to FKW fkw@cithe502.cithep.caltech.edu